Micro-interconnects: Signal integrity in 5G applications

05. December 2019, 2:05PM – 2:35PM
Location: 3813
Authors: Sarangapani Murali and Wong Chin Yeung Jason
Mode: Invited presentation

This presentation deals with two aspects on micro-interconnects in semiconductor packaging. First, recent developments in wire bonding, soldering, sintering primarily designed for low electrical resistivity are reported. Second, these wire-bonded, sintered and soldered structures satisfy low loss in transmitting wide bandwidth signals in 5G applications are discussed.

In bonding wire technology, bare and palladium coated copper wires have positioned themselves in high volume replacing gold bonding wires successfully. Alloyed silver wires are used in LED. Gold coated silver wires are studied for memory applications using cascade bonding method. Low temperature bismuth-tin solders have been examined for the last few decades and currently are popular in the usage to reduce warpage (zero) and electrical power consumption. The reflow temperature of these solders are aimed to be less than 190°C. Sintering with nanoparticles reduces process temperature by rapid necking. Using bi-modal electrically conductive powder particles and composite materials, Heraeus-innovation team explores sintered interconnects to process with low reflow/sinter temperatures. In addition, the sintered interconnects possess low insertion losses with good signal and power integrity. The talk concludes with a challenge to researchers to develop new interconnect materials without limiting the boundaries between electrical resistivity and high-volume production, while still aiming to innovate micro-interconnects with unified performance that blends signal integrity with low insertion loss and low electrical/thermal resistivity.